The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller feature sizes and more complex circuits than those from the previous generation. These advances are made in pursuit of higher device density, higher performance, and lower costs. As this technological progression takes place, conventional lithography alone may not be able to satisfy the increasingly stringent demands of design rules. As a result, various patterning techniques have been developed to help push the limits of lithography. However, even these patterning techniques may not be able to sufficiently address the challenges brought by three-dimensional transistor devices, such as fin-like field effect transistor (FinFET) device. In that regard, a typical FinFET device is fabricated with a thin “fin” (or fin-like structure) extending from a substrate. The fin usually includes silicon and forms the body of the transistor device. The channel of the transistor is formed in this vertical fin. A gate is provided over (e.g., wrapping around) the fin. This type of gate allows greater control of the channel, reduced short channel effect, and higher current flow. However, FinFET devices may also require stricter End to End (ETE) critical dimension (CD) control for contact landing. These requirements have not been sufficiently met by conventional lithography or the various patterning techniques that exist today.
Therefore, while existing methods of fabricating advanced semiconductor devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.